Field of the Invention
The present invention relates to a calculation device. Priority is claimed on Japanese Patent Application No. 2013-236904, filed Nov. 15, 2013, the content of which is incorporated herein by reference.
Description of Related Art
In an LSI (Large Scale Integration) design, a scheme called resource sharing in which a common process is extracted from a plurality of processes and a circuit that performs the common process is shared so as to suppress increase in a circuit is generally used. In this scheme, for example, when two multiplication operations are included in one process, one multiplier (resources) can be shared through shifting of respective multiplication execution timings. Adjustment of this process execution timing is called scheduling.
In such a resource sharing scheme, reduction of power consumption is desired. A scheme of sharing resources of an exclusively operating processing unit by scheduling and stopping a clock of a processing unit that does not operate to thereby reduce power consumption has been proposed in Japanese Unexamined Patent Application, First Publication No. 2008-282360.
In an actual circuit, there is a case in which a period of time required for one process is changed every use case (operation situation). Further, when a low-speed process is performed, suppression of peak power is desired. However, in the scheme described in Japanese Unexamined Patent Application, First Publication No. 2008-282360, an operation is fixed according to scheduling for the fastest processing within an assumed use case.
FIGS. 13A and 13B show an example of scheduling for the fastest processing in the scheme described in Japanese Unexamined Patent Application, First Publication No. 2008-282360. In FIGS. 13A and 13B, a horizontal axis indicates time, and a vertical axis indicates power. The unit of the time in FIGS. 13A and 13B is a cycle corresponding to a period of a clock supplied to a circuit. FIGS. 13A and 13B show examples of scheduling of a calculation device having four multipliers.
FIG. 13A shows an example of scheduling in which eight multiplication operations are performed in two cycles. An operation in one cycle in which four multipliers operate in parallel is repeated twice, and thus eight multiplication operations are performed in two cycles. In FIG. 13A, a state is shown in which two cycles in which eight multiplication operations are performed are repeated. In FIG. 13A, peak power (Pmax) is the power needed when all multipliers included in a calculation device operate in parallel.
FIG. 13B shows an example of scheduling in which eight multiplication operations are performed in four cycles. Since the scheduling is performed such that processing is fastest, four multipliers operate in parallel in two cycles. Accordingly, the eight multiplication operations are performed in two cycles. After a period of two cycles in which four multipliers operate passes, the four multipliers stop for the next two cycles. A state is shown in FIG. 13B, in which two cycles in which eight multiplication operations are performed when the four multipliers operate in parallel and two cycles in which the four multipliers stop alternately appear. In FIG. 13B, peak power (Pmax) is the power needed when all multipliers included in the calculation device operate in parallel.
As described above, in the scheme described in Japanese Unexamined Patent Application, First Publication No. 2008-282360, even when the number of cycles in which a predetermined number of calculations are performed is changed, the peak power becomes power when all multipliers included in the calculation device operate in parallel.